Design And Implementation Of Fpga-based High-speed Data Transfer And Storage System

Synthetic Aperture Radar (SAR) is a kind of high-resolution imaging Radar. Using SAR we can obtain high-resolution Radar images under all weather, day and night, and long distance conditions. With functions of radar is complicated more and more, the amount of echo data is required more and more, and the traditional echo simulator is parochial at the aspects of the velocity of echo data and the storage, this thesis studies the velocity of echo data and the storage. In the traditional method, many engineering applications often use multi-chip high-speed DSPs to implement in parallel mode. But in recent years, with the development of integrate circuit and programmable devices, the FPGAs become better than the DSPs at the aspects of the processing speed,hardware resources and flexibility. Base on the advantage of FPGAs, we put forward a system structure of"PC +FPGA". And we store the echo data with Serial ATA hard disk and SDRAM, not only solve the issue of storage, but also solve the issue of velocity.The SAR echo simulator designed in this thesis includes four work modes, such as SAR1m,SAR5m,DBS1m and HM3m. And we first produce the echo data in PC, and transmit them to the echo simulator controller by USB bus, then store them in SATA hard disk, and then the SATA controller serves as the"host computer". The decoding of the work modes and the processing wok of the echo data are implemented in the FPGA chip. And we store the echo data with the SATA hard disk, and store echo data to and read echo data from the SATA hard disk with SDRAM"ping pong"operation, then read corresponding echo data from SATA hard disk according to the decoded work mode and store them in the SDRAM with"ping pong"operation, then transmit continuously the echo data in a frequency of 250MHz, the width of which is 24, once a PRF is detected. The following issues are mainly discussed in the thesis:First, the thesis introduces the background of the technology of the radar echo simulator, and then introduces the realistic meaning.Second, According to the requirement and the technology guideline of the system, the design of the scheme of SAR echo simulator controller is determined, and then the feasibility is demonstrated. Third, According to the system design, the hardware design of SAR echo simulator controller is implemented, including the chip selections and circuit design.Finally, According to the requirement of the system, the FPGA's development and debugging and the work of the echo data are implemented, including the design of the interface between FPGA and USB bus, the design of the interface between FPGA and RS232 bus, the design of RS232 protocol, the design of SDRAM controller, the design of"ping pang"operation between SDRAM and SATA and the design of the decoding of the work modes. And the method of"ping pang"operation with SDRAM is introduced,then the timing design of the whole transmitted course of the echo data is implemented.