Low-jitter, Self-calibrated Phase-locked Loop Design

Nowadays in semiconductor industry, analog circuit design is much more difficult due to the minimum length and power supply become low. At the same time technical miss match cannot be ignored. So calibration technical is widely used in PLL, ADC circuit. PLL's accuracy is very important for systems that need clock.This paper's goal is an algorithm to select an optimal sub-band in self-calibration circuit, and save area and power by close loop without bias voltage or bias current. In the optimal sub-band, then the smaller gain brings better jitter and phase noise which we care about. Small area and power is popular too. Also the control bit is select by loop itself, so the effect from change of power, temperature and process can be much more reduced.The most different thing in this design is to get the optimal performance by simple algorithm. Layout is also a challenge, because mix-signal circuit need to be careful in noise isolation. So dose each block of PLL.We use SMIC 0.13um logic process to do MPW. Then test the chip, rms jitter is low than 10ps, and phase noise can reach-131dB in 1M offset.