Scan Chain-based Fpga Interconnect Test

In the begin of this thesis, we make an analysis on structure of SRAM-based FPGA, especially on interconnect structure and resource. The concept of DFT is introduced in the next word. Involving fault model, scan chain, and post full scan, we present what should be considered when we accept DFT in ASIC design flow. The test of FPGA are classified into different class based on the circumstance of testing, the target of testing and the method of testing. The characteristic of every testing is explained in the thesis.Here, we focus our work on the testing of interconnect resource. With accepting the concept of Buffered-WUT, we will test interconnect resource in FPGA based on post full scan. Buffered-WUT is used to reduce the count of test CONFIG. We use the programmable logic resource in TILE to build scan chain. Based on the direction of switch in GRM, we classify the testing into horizontal testing, vertical testing, left diagonal testing and right diagonal testing. We worked on horizontal testing.In my work, the original FPGA circuit is modeled to gate-level netlist in verilog format. And, the gate-level netlist is uniquified based on TILE. Then, according to the different testing CONFIG, the gate-level netlist is remodeled into several different netlist. At last, with using TurboScan tools from SYNTEST, scan chain extraction, test pattern generation and test bench generation are operated. Test pattern verification is operated on the netlist after uniquify.The report of scan chain extraction shows that there are 2 scan chains in one line of TILEs and each chain has 95 Scan-FFs. ATPG report shows that, under testing CONFIG 1, the fault coverage got by 7 test pattern is 84.53%. This result proved that except the fault in corner, all the faults are covered under CONFIG 1. And the other 2 testing CONFIG will cover the fault in corner.