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Study On Adaptive Algorithms For Diagnosis Of Interconnect Resources Of FPGA

Posted on:2006-08-30Degree:MasterType:Thesis
Country:ChinaCandidate:Y JiaFull Text:PDF
GTID:2168360155468951Subject:Computer application technology
Abstract/Summary:PDF Full Text Request
Field Programmable Gate Array (FPGA) is a kind of field programmable ASIC, what combines the structure in common use of gate array and the field programmable characteristics together. Now, the FPGA series devices are becoming one of the most popular devices. With the rapid development of FPGA, the density and complexity of FPGA are higher and higher, making a large number of faults difficult to use the traditional method to test, requiring FPGA designers to consider the problem of design-for-testability (DFT). Because the faults taken place in interconnection resources in FPGA have greater frequency than that in logic resources, FPGA devices of nearly all companies have offered the ability of boundary-scan design-for-testability, and FPGA devices apply to the departments requiring high dependability, such as aviation, spaceflight, etc. in a large amount, so it is necessary to carry on research about maximal diagnosis of FPGA interconnection resources based on boundary scan architecture.This paper introduces the structure characteristic and testing technique of FPGA devices, and the principle structure and theory of boundary scan test at first. Then this paper gives testing optimization strategy and proceeds thorough research on adaptive algorithms for maximal diagnosis of interconnect resources on FPGA devices based on boundary scan testing technique. During the process of the research, the paper analyzes the performance of original adaptive algorithms based on the thought of adaptive maximal diagnosis, and imports the concepts of the independent test set and the testing matrix into original adaptive algorithms. This makes the improved optimization algorithm simplify the realization process of original algorithms and achieve the goal of maximal diagnosis. Finally, this paper designs and realizes a set of test emulation model making use of ISE6.2 EDA development environment of Xilinx Company and ModelSim emulation software, and utilizes this model to prove the optimizationalgorithm. Theoretical research and simulation experiments both show that the optimization algoritlim can achieve the goal of maximal diagnosis, and has some improvement in the compactness and complexity of test.
Keywords/Search Tags:FPGA, Interconnect, fault diagnosis, boundary scan test, adaptive diagnosis
PDF Full Text Request
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