The Research Of On-chip Circuits Evolutionary Design Based On FPGA

With the development of society and the progress of science and technology,the circuit system tends to be miniaturized,intelligent,The scale and complexity of circuit system are increasing.At the same time,the reliability of circuit system has become a great challenge in the development process.The emergence of hardware provides a solution.Evolutionary hardware is an organic combination of evolutionary algorithms and programmable logic devices.It can adapt itself to the environment according to the changes of the environment,dynamically adjust its structure,improve the stability and reliability of the hardware in the harsh environment,and prolong the service life of the hardware.Field Programmable Gate Array(FPGA)as the latest development of programmable devices,with flexible,infinitely reconfigurable features,is widely used as the realization of evolutionary hardware carrier.The evolutionary algorithm and the evolutionary hardware circuit on the same FPGA constitute the on-chip evolution system,which is an important way to make the evolution of hardware into engineering applications,constitute an adaptive and fault-tolerant hardware system.In this paper,the realization principle and key technology of evolutionary hardware are studied,and an on-chip evolutionary design platform composed of NiosII embedded soft-core processor,VRC virtual reconfigurable circuit decoder and on-line evaluation communication module is designed on the FPGA.The platform can be carried out on-chip circuit evolution design.The main research contents are as follows:1.The evolutionary design of circuit is studied by using Cartesian genetic programming CGP as evolutionary algorithm.The relationship between chromosome mutation rate and evolutionary convergence rate is studied,and the optimal number of variants is obtained under given gene length.2.The FPGA-based on-chip circuit evolution design platform is studied.On the FPGA chip using the design of NiosII embedded soft-core processor CPU,virtual reconfigurable circuit decoder VRC,online evaluation of communication module.NioSII embedded soft-core processor CPU implementation of the evolutionary algorithm,through the evolution of a new generation of population generation;VRC virtual reconfigurable circuit decoder to each of the chromosomes in the population decoding,and FPGA chip automatically constructed with the chromosome phase Corresponding to the circuit;online evaluation of the communication module to achieve through the construction of the circuit data collection,and real-time feedback of the data back to the NiosII soft-core processor,to achieve the circuit on-line evolutionary design of the circuit.And the on-chip evolutionary design experiment of on-chip circuit is proposed for the full adder and multiplier.3.The on-chip evolutionary design of synchronous timing circuits is studied.The VRC virtual reconfigurable circuit module of the evolutionary timing circuit is constructed by adding the D flip-flop to the VRC virtual reconfigurable circuit decoder for the evolutionary combinational circuit.The on-chip evolutionary design of the sequential circuit is realized by evolution.The evolutionary design of modulo six counters and 1010 sequence detectors is carried out.