Qpsk, If Digital Demodulator Design And Fpga Implementation

With the rapid development of the digital signal processing technology and large scale integrated circuits, as well as the widely use of software radio technology, all-digital IF demodulation technology has been further developed in wireless communications and been widely applied.This paper briefly introduces the basic principles of QPSK digital modulation, mainly a study of the QPSK-based digital IF demodulator design and FPGA implementation. The design given in this paper applies frequency offset estimation algorithm using fast Fourier transform (FFT) for the large frequency offset correction when digital down conversion. Theoretical analysis and simulation by MATLAB are taken to verify the feasibility of the algorithm. The carrier phase tracking and bit synchronization algorithm is also carried out a similar analysis, computer simulation has been through the algorithm for SNR loss. Then the algorithm is converted to HDL description for FPGA realization. The designs of the core modules of demodulator, including digital down-conversion, carrier ring, bit synchronization loop design, are described in detail. And a block diagram and simulated waveforms are provide in the latter part. Also the soft-core processor technology of Altera's Nios II is applied in the design for carrier frequency offset correction and the monitoring and control of the separate parts of demodulator. Finally, the test methods and results of key performance indicators of the IF Demodulator QPSK are given to show that the design given in this paper can reach the performance requirements expected.At present, the project of the design and FPGA realization of all-digital QPSK demodulator has been successfully passed the inspection and completed the handover.