.bpsk / Qpsk Signal Digital To Resolve The Research And Design Of The Tune

In traditional digital communication systems, the demodulation cells of receiver were realized with analog manage means and chips. The sorts of traditional receivers can't exert the predominance of digital communication completely and also can't realize the optimal receive of digital communication. So, we bring forth a sort of complete digital demodulation project based on the STEL-2105 chip, which is to suit the request of the modern high-speed developmental data communication. This paper dealed with the project that the complete digital demodulation of QPSK signals, adopted the advanced DSP control and applied some new software technologies, mainly include Analog-to-Digital converter,digital down converter,integrate and dump filters of digital IF and carrier synchronization,symbol synchronization of digital demodulation, and so on. Its characters are integration of software and hardware, the system's calculation is small, and it is easy to be implemented using DSP (TMS320VC5409). First, this paper depicted conception of software radio and characteristics of complete digital demodulator. Then, correlative researchres about some key technologies of complete digital demodulation, especially carrier synchronization and symbol synchronization are discussed in detail. The author's main productions and contributions are as follows: (1)The method of complete digital demodulation of BPSK/QPSK signals are studied and proved. It combines the demultiplexing circuit with the algorithm of demodulation. So the conception of integral demodulation can be reached. And the whole system is realized by the high-speed DSP, so that the complete digital demodulation of BPSK/QPSK signals can be practical. (2)The relational two projects about carrier synchronization and a kind of new Symbol Timing recover symbol synchronization are discussed. One project is to control and adjust the NCO with the AFC and the PLL signals. The other is to control the dump filters and the symbol accumulator respectively with a SAMCLK and a SYMCLK. So the sampling rate of signal is synchronized to the symbol rate for further processing.