| Early, power output devices and logic control part on the system board, is separated by printed circuit board (PCB) with connected together.The disadvantages are excessive power consumption, very low integration and poor reliability. With the continuous development of integrated circuit technology, and increasingly smaller and low power consumption of hand-held portable devices,as a result, the power integrated circuit technology is emerging.The main objective of the paper is to investigate parallel output stage structure and process of high voltage devices. Firstly based on the standard CMOS process, this paper analysis several options, and compare these from the cost of process reform, difficulty and feasibility. To obtain a set of standard HV-CMOS technology for the process reform, this paper uses process simulation software ATHENA for process simulation. Then, based on the improved HV-CMOS process, this paper uses device simulator MEDICI to achieve different double RESURF LDMOS device structures, and characteristic simulation was carried out. As the LDMOS high-voltage interconnection line will greatly affect the breakdown voltage of the device, this article uses self-shielding structure high-voltage interconnect according to the needs of implementation level shifter of half-bridge converter circuit, and designs the device layout. Finally, the paper analysis the steady-state electric-thermal model of the parallel power MOS devices, and the effects of threshold-voltage & resistance mismatch on the parallel power MOS current imbalance.In summary, the completed work as follows:1. High-voltage process compatible with the standard CMOS process-Improved HV-CMOS Process;2. Design and optimization different structures of high-voltage (> 600V) LDMOS devices;3. Analysis the steady-state electric-thermal model of the parallel power MOS devices, and the effects of threshold-voltage & resistance mismatch on the parallel power MOS current imbalance. |
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