Block Parallel Dbf Algorithm And Its Implementation

With the development of signal processing technology, adaptive digital beam forming has played important roles in both military and commercial application fields, such as radar, communication, and so on. With the technology of adaptive digital beam forming (DBF), radar can cancel active interference. This thesis is focused on the study of DBF algorithms. The main work includes:1) Based on the advantages of FPGA and PowerPC, FPGA + PowerPC configuration of DBF processor is proposed, which can meet the requirements of real-time and Large amount of computing.2) As the widths of data are limited, when DBF algorithm is implemented on FPGA, a method of data cut-off should have been taken. Structure of hardware implementation of SLCMV algorithm is simulated with MATLAB, and a reasonable method of data cut-off has been found.3) SLCMV algorithm is divided into two parts depending on its feature. First part includes a large number of complex multiplications and complex additions. This part is implemented on FPGA. Second part is used for computing step length,constrained vector and so on. This part is implemented on PowerPC405.4) A hardware platform of PowerPC is built, including PowerPC405,General Purpose Input Output(GPIO),PLB BRAM Interface Controller,RS232. Data transmission between FPGA and PowerPC is available. Debugging and testing of hardware system are finished. Hardware system is proved to be effective by comparing results of hardware and the ones of MATLAB.5) Comparing with serial program of SLCMV algorithm which runs on PowerPC, the parallel program runs 5138 times faster.