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The Research On Design For Testability Of FPGAs

Posted on:2007-07-18Degree:MasterType:Thesis
Country:ChinaCandidate:J J WuFull Text:PDF
GTID:2178360215458290Subject:Computer application technology
Abstract/Summary:PDF Full Text Request
Field Programmable Gate Array (FPGA) is a new kind of device, what combines the structure in common use of gate array and the characteristics of field programmable together. Now, the FPGA serial devices are becoming one of the most popular devices. With the extensive application of FPGA, the function in the digital system is more important. So, the more overall research on the fault testing and diagnosing is significant. With the fast expand of the scale of the integrated circuit, the structure of the circuit becomes more complex, which makes numbers of defaults are not easy to test, requiring FPGA designers to consider the problem of design-for-testability (DFT). The proposition of the problem of design for testability offers a new effective way to solve the problem of testing, and one of the important technologies of DFT is boundary scan test.This paper introduces the structure characteristics and testing techniques of FPGA devices, and the principle structures and theories of boundary scan test. The mathematics descriptions and mathematics models of BST utilizing the matrix theory are given. First, the problem of test optimizing in the BST is discussed, and the existing arithmetic which solves two kinds of optimization problems is provided. This paper analyzes their advantages and shortcomings, puts forward improvements to two kinds of existing algorithms, and compares the performances of both optimization algorithms that before and after being improved. In addition, this paper gives testing optimization strategy and process thorough research on adaptive algorithms based on boundary scan testing technique for maximal diagnosis of interconnect resources on FPGA devices. During the process of the research, the paper analyzes the performances of original adaptive algorithms based on the thought of adaptive maximal diagnosis, and injects the concepts of the independent test set and the testing matrix into original adaptive algorithms, which makes the improved optimization algorithm simplify the realization processes of original algorithms and achieve the goal of maximal diagnosis. Finally, this paper designs and realizes a set of test emulation models to show that the optimized algorithm has some improvements in both the compactness and complexity of test, and can achieve the goal of maximal diagnosis more effectively.
Keywords/Search Tags:FPGA, design for testability, fault diagnosis, boundary scan test, adaptive diagnosis
PDF Full Text Request
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