H.264 Decoder Based On Tms320dm642 And Implementation

The new generation video coding standard H.264 which was proposed by ITU-T and ISO/IEC international organization, is being more and more extensively applied and researched in the filed of industry and academic because of the advantages such as: high data compression ratio, good network adaptability, strong anti-error characteristic, and so on. But at the same time, the huge amount of code and very high computational complexity of H.264 encoder and decoder not only has a high requirement on the platform performance, but also greatly increase the difficulty of real-time implementation. The new generation digital media processor TMS320DM642 (DM642 for short) was Launched by Texas Instruments Corporation. It has provided a good platform for video real-time decoding with the features of quick processing, strong parallel processing ability, special audio and video interface, EDMA channel, and so on. The implementation and research of H.264 decoder based on DM642 has important significance on platform of multimedia communication terminal, also has potential of market applications.In this thesis, the effective implementation of H.264 decoder based on DM642 has been analyzed. Then key modules of decoder that greatly affect efficiency are improved and optimized on the basis of deep analysis of H.264 decoder algorithm and DM642 hardware architecture.The main results are as follows:1. Constructing software architecture of H.264 decoder on the platform of DSP DM642. Transplanting the H.264 decoder from PC platform to DM642, so that the new decoder in line with the program structure and storage distribution of DM642. Then compiling, linking, running the new decoder on the new platform.2. Computational complexity and storage space consumption of H.264 decoder has been analyzed deeply. Time and storage consumption of decoder has been analyzed by the tools of TI CCS profile, and then finding out modules that severesly affect decoding efficiency for next improvementation and optimization on DM642.3. The optimization and implementation of H.264 decoder based on DM642. A series of optimized measure are carried out when understanding the algorithm of H.264 decoder and combinning the structure characteristics of DM642. Those measures include algorithm improvement, adjustment of program structure, reallocation of decoder storage space, linear assemble language and so on.4. Display of video sequence and system testing. The decoded video sequence is outputted and displayed on TV through the video port of DM642. Finally, testing the optimized decoder and making detailed comparison with the decoder on PC platform on the aspects of decodig speed and efficiency.After the above-mentioned work, H.264 decoder based on DM642 has already rightly worked and outputted. The decoding speed of QCIF video sequence can reach to about 46.3fps, which can meet the real-time requirement.