Research On The Key Technology Of Router Buffer For NoC

Network-on-Chip(NoC)implements the interconnection between multiple IP cores in a chip.The research of NoC technology has many aspects.Particularly,the router buffers occupy most of the network's area and power consumption.The size of buffer has a significant impact on network's performance.So the buffer technology research plays an important role in the study of NoC.This dissertation attempts to research from dynamical allocation multi-port buffer,multi-queue adaptive buffer and multi-queue combined buffer.On the basis of the existing NoC buffer technologies,aiming at the blocking problem when input port compete for buffer,this dissertation proposes a buffer allocation technology based on multi-port resource competition.Aiming at the complexity of dynamically allocate multi-queue of virtual channel and large hardware overhead,this dissertation proposes an adaptive buffer technology based on single port multi-queue.In order to avoid the waste of resources,reduce the chip area and ensure that the data can transmit correctly,this dissertation proposes a combined technology based on Flexible buffer and FIFO.Main work and contributions of this dissertation are outlined as follows:1.A buffer allocation technology based on multi-port resource competition.In the router structure composed of this buffer technology,the input ports use FIFO-Dynamic-Allocator to allocate buffer dynamically.When a port has resource competition,FIFO-Dynamic-Allocator can check other adjacent ports if there is a free buffer can be used.A VC-Recorder is added in every input port to record the occupation of virtual channel.Experimental results show that,compared with other input buffer router,the throughput of this router is higher and the average latency is lower.2.An adaptive buffer technology based on single port multi-queue.In the router structure composed of this buffer technology,the transmission of a flit consumes only one clock cycle.The input port uses the same mechanism with DAMQ input port for dynamically flow control.At the same time this router uses the IRR arbitration which consumes less hardware.In IRR arbitration,when a signal sent to an input port is lost or there is no output signal,IRR arbitration would be blocked.Experimental results show that,this router consumes lower hardware,have higher throughput and lower average latency.3.A combined technology based on Flexible buffer and FIFO.In the router structure composed of this buffer technology,the multiple virtual channels of an input port use two different buffer structure,Flexible buffer and FIFO.Packet is stored separately by length.Due to the Flexible buffer is simple and easily control,it can reduce the router area significantly.In order to ensure a packet arrive to the destination successful,an error detection mechanism is used.