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Research On The Large-capacity-buffer Mechanism Based On The 10G Output Interface Of The T Bit Router

Posted on:2007-04-22Degree:MasterType:Thesis
Country:ChinaCandidate:S B YangFull Text:PDF
GTID:2178360212475718Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
Along with the explosive expansion of the traffic carried by the Internet and rapid growth of the network scale, the 10G-interface of the router will become one of the main interface types in the future. In addition the business in the network presents the tendency of the diversification. The various businesses have the different requirement in the buffer capacity, and some hot spot business particularly needs the large capacity buffer to carry. At the same time the diverse business also needs different quality of service (QoS). Therefore it is needed to set the high speed and large capacity buffer in the T bit router to meet these demands.This paper mainly studied the design implementation plan of the large capacity buffer mechanism based on the 10G-interface which was located in the output ports of the T bit router. The high speed large capacity buffer mechanism was systemly researched and analyed from the design of the buffer structure, the managed mechanism of the queue and the scheduled mechanism of the queue. The design plan of the large capacity buffer based on the 10G interface which was located in the output ports of the T bit router was proposed, and was implemented through hardware electric circuit.This paper's contribution mainly included the following several points: The steady work condition of the parallel distributed buffer architecture (PDBA) has proved in theory. And the formulae were obtained about the speed and the apacity of the PDBA sub- level buffer.Proposed one kind of the new queue congestion control mechanism - different service in the random early detection (DSRED). Compared to others, the DSRED was able to guarantee different loss rate for the various business in the every phase of the congestion avoid. Therefore, the DSRED was able to support different service for the various businesses. Proposed one kind of the new scheduled algorithm - smooth output weighted deficit round robin (SO-WDRR).Through the introduction of the deficit and fair insertion mechanism, the SO-WDRR algorithm has solved unfairnesses which were cased because of the various length of the IP packets and the different weight value in the different queue, improved the delay, smoothed the outburst intensity, reduced the buffer pressure of the next router. The SO-WDRR algorithm was also proved to may obtain the good performance through the theoretical analysis and the simulation experiment.Because of the different needs for the various businesses in the QoS, further proposed the scheduled algorithm-different service in the SO-WDRR algorithm (DSSO-WDRR). Besides inherited the SO-WDRR algorithm merit, this algorithm was able to support the different QoS...
Keywords/Search Tags:T bit router, buffer mechanism, buffer architecture, management of the queue, schedule
PDF Full Text Request
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