Realization And Optimization For H.264 Video Decoder Based On DSP TMS320DM642

H.264/AVC is the newest video coding standard of the ITU-T Video Coding Experts Group and the ISO/IEC Moving Picture Experts Group.As a video coding standard for next-generation multimedia,H.264/AVC adopts a number of advanced technologies different from the previous standards.In addition to improved coding efficiency and coding performance,these technologies add the complexity of H.264 Coder and limit its practical use in many areas,particular in real-time system.So there is theoretical meaning and practical value to optimize video coding and decoding algorithm with the limited on-chip memory space in embedded environment.Because of the far speed and the low consumption of resources,DSP has outstanding performane in many areas.The TMS320DM642 device is a fixed-point digital signal processor(DSPS)based on the second generation high-performance very long instruction word(VLIW)VelociT1.2 developed by Texas Instruments(TI).It extended instruction set for a special video/image processing,enhanced video processing parallelism.At a clock rate of 600MHZ,the DM642 device can perform up to 4800 million instructions per second(MIPS).The DM642 Digital Media Processor has a number of Peripheral Interface Chip,it is suitable for the video and imaging applications,for example,the audio/video transmission and security monitor over IP and wireless networks.The main task of this thesis is to develop and optimize H.264 decoder software on the Texas Instruments' TMS320DM642 Digital Media Processor.The thesis firstly makes a thorough introduce of H.264 standard,then analyzes and modifies X264 decoder on the PC platform,migrates and optimizes the decoder on the DM642 platform at last.The work includes several parts:to reduce,modify the source program and migrate it from PC to the DSP platform;to improve the algorithm and code using optimization options,intrinsics and linear assembly language,which can improve the parallelism;to optimize the code considering the character of two level Cache structure of DM642 chip.Our H.264 decoder can decode 35～50 frames per second(fps)for QCIF resolution video by redesigning and optimizing,achieving the real-time decoding of QCIF video sequences basically.