Fully Parallel Fpga Implementation Of Viterbi Decoder

This thesis mainly focuses on the design of parallel Viterbi decoder and its FPGA-based implementation. The decoder is applied to a digital communication moderm of a project.At first, the basic principle about convolutional code and Viterbi decoding algorithm are introduced, and the analysis of the error correcting performance is given. After that, we introduce some classic algorithms about the realization of a parallel Viterbi decoder. For these algorithms' realizations, we also discuss about the hardware optimization. Then, a test module to verify the results of the Quartus's simulation with Matlab languages is built. In the end, the bit error rate (BER) performance of the actual system is listed.According to the result, the BER performance meets the requirements of the project, and it also testifies the validity of the parallel design. And the decoder designed here can also be used in a high-rate communication system.