Based On The Soc On-chip Bus Ip Plug And Play

In the SoC(System On Chip)system design, IP reuse and system verification is the key to SoC design, the ultimate vision of the IP reuse is plug-and-play, so that it not only make use of IP but also accelerate the SoC system verification, thereby reducing SoC chip's time-to-market to seize the market opportunities.This thesis is about IP Core Plus-and-Play Based SoC system Bus, through analysing the problem in the design of SoC system and pointing out that the solution to the problem is the IP standardization and plug-and-play, further analyzing on international standardization about protocol of IP plug-and-play, and selecting OCP (Open Core Protocol) IP protocol which is perfect and tested by the market to research, then finding a way to package IP automatically and to verify OCP IP cores and designing related software and hardware.This thesis firstly introduces the IP standardization and the technology about design and verification, analyzing some problems in SoC systems such as problems in IP reuse and system verification because bus selecting and changing. Then it introduces OCP IP protocol detailly, including the OCP IP system architecture, OCP interface which based on point-to-point transmission and can be reconfigured, as well as the principles of IP plug-and-play and profiles required in IP standardization. And thesis introduces system bus interfacing with OCP IP standardization core, ARM's AMBA bus and the Silicore organizations's Wishbone bus. Then discussing the electromagnetic compatibility of 12 layers PCB board, including transmission line effect, impedance matching, the way to rout match lines in FPGA, and the method to rout differential Lines and so on. Then introducing the design of the OCP package software and the software's processflow.Finally, as the controler of SDRAM memory IP core for an example, the IP core after OCP IP software packaged is articulated at AMBA and Wishbone system for the purpose of the IP plug-and-play and verifying quickly.