| SOC(System on Chip) technology has evolved as the pre dominant circuit design methodology. The entire system's functionality is implemented on a single IC. This IC may integrate digital, RF, analogue and other functions. The advantage is that SOC technology moves design from the circuit level to the system level, concentrating on the selection of appropriate IP blocks and their interconnection into a complete system. An IP core based system can be viewed as a collection of various IP cores with an interconnection bus running among them.The network of self-contained IP cores may suffer from stable failures such as deadlock and livelock. Only a fundamentally correct design method provides a reliable way to avoid deadlock and livelock problems. One of these methods is a synchronization method which is robust and simple enough to be applicable to almost every digital design. The synchronization scheme can leads to abstract models which are comprehensible enough to be understood and proved. The CSP (Communicating Sequential Processes)theory is based on the synchronization. It emphasizes the sequential performance. And the CSP design method can provide the abstract of the different level. Such as: System level, Chip level and so on. It is very helpful for designer to analyze and design the process.Viterbi algorithm is one of most famous decoding algorithm for convolutional code in communication field. By reading abundance other people's research literature, this paper comprehends Viterbi decoding algorithm deeply.. And it provides the appropriate structure for the decoder of the DAB convolutional code. Then it describes the decoder based on the CSP theory. For implementation, the Viterbi decoder is implemented on FPGA by using ISE design platform of Xilinx to design VHDL program, synthesis, simulate function logic and simulate time logic. |
