Research Of Low Power Methodology For Real Time Reconfiguration Of Resources In FPGA

On the base introduction of the principal technology of FPGA dynamic reconfiguration and methods of low power in IC circuits, the importance and imperious requirement for low power in dynamic FPGA reconfiguration are stated ,which methods are different levels from physical ones, gate ones ,c'ircuit ones ,system ones to abstract ones.After detail discussion and research for various levels ,a full set of low power methodology for application of basis of dynamic FPGA resources has been formed and basically a initial theory system has also been formed.To begin with basic general low power methods,general methods ,approaches and measures are introduced . Resources and structures of FPGA then combined and the developing trend of its new structures ,furthermore as to more high requirements that is for dynamic reconfiguration in order to explore and research a approach and methodology of the newest low power estimation suited for dynamic FPGA reconfiguration technology .In process of the thesis ,some statistic ways such as possibility ,capacitance model and switch activity have been introduced ,using a new way to estimate the dissipation of VLSI FPGA structures ,what is more ,in the case of utilization of dynamic FPGA resources ,statistics seems especially important and efficiency during the analysis .In the thesis we have adopted some analysis EDA tools ,mainly VPR(Versatile Placement and routing) and VPACK (Versatile Packing) ,and statistics models are embedded in the EDA analysis flow.With analysis and comparison ,porting and improving those methods so as to be suit for requirements of environment for dynamic FPGA reconfiguration, a perfect low power methodology for dynamic FPGA reconfiguration has been come out and it has been proved its efficiency after theory examination ..It is concluded that those approaches and methods are actual and practical .Also some main aspects like area,speed and power dissipation of circuit system are all substantially improved.The brief jobs of this doctoral thesis are as following:First of all,the composition for CMOS circuit and its corresponding power dissipation model have been analyzed, and the methods for static and dynamic power estimation are also summarized.Secondly,analyzed the architecture of FPGA' and its dynamic re-configurable mechanism,adopted the research for distribution of routing tracks in FPGA which utilize traditional simulating anneal algorithm.According to the results of different distribution of routing tracks in FPGA,taking into account the effect of logic implementation in FPGA to reach the aim for lower power dissipation. Thirdly,combined the architecture of FPGA and the methods of efficient lower dissipation,after analyzing and practicing on them,one capacitance-base model has been created and integrated with statistics,a primary low power dissipation method for FPGA resource reconfiguration has been realized.It means that the designers may modify the design of project according to the low power estimating results and lessen the power dissipation for whole circuit system by designing special circuit modules that are relative to power reduction.Fourthly,with analysis for dynamic FPGA resource reconfiguration,modification for estimation model of low power dissipation has been undertaken.One suitable low power estimation model for dynamic FPGA resource reconfiguration is put forward and a low power dissipation methodology is achieved.On account of the methodology is tightly linked with the architecture of FPGA,in the whole methodology it is no doubt that this would bring many new thought,suggestion and instructions for research of FPGA architecture.Thereby, some discussions about those are introduced at the end of the thesis and what next jobs on the subject will be.