Design Of Serial Interface Engine Of Host Controller Based On Universal Serial Bus 2.0 Protocol

Nowadays, USB2.0 is the most prevalent interface standard of peripheral equipment. Embedded USB2.0 host will be used in portable devices widely along with the coming of 3G era. USB2.0 host is the center of USB2.0 system's topology, and host controller is even the hinge of it. This paper has achieved the IP soft core designing of serial interface engine (SIE), which applied in Embedded USB2.0 host controller.First of all, the study significance and background of USB2.0 are introduced, the system structure of USB2.0 is described and the protocol criterion of it is given. Secondly, the function of serial interface engine (SIE) in host side is analyzed on the basis of having known the protocol well, and SIE is parted into seven modules with the Top-Down designing method: digital clock recovery, decoding, disassemble packet, CRC verification, assemble packet, coding and bus time counter. Then they are described with Verilog Hardware Description Language in RTL level. Thirdly, the test bench is designed and the whole SIE is simulated in Ncsim software. The result shows that the SIE designed in this paper has completed all functions described in USB2.0 protocol and fulfills the timing request.Finally, the logic synthesis and timing analysis are implemented on the SIE in QuartusII software with FPGA Stratix serial chip EP1S10F484C5 of Altera company, and the synthesized circuit diagrams are given.