Fpga-based H.264 Video Compression Encoder

H.264 video compression standard is widely used in fixed or mobile video phone, mobile phone, video conference, video monitor, IP streaming media, Internet video, mobile television, broad band telephone, video storage and so on. H.264 video compression standard just defines the encoder block diagram, but not the algorithm. Consequently, scholars and engineers have based on the encoder block diagram to use the adaptive algorithm to design it, and continued to explore the lower complexity algorithm as well.Based on the system diagram and the relative algorithm, work to study the implementation of the encoder has been carried out deeply and the results-IP cores, can be applied in the I frame module of 'The Implementation of The H.264 Video Compression Encoder'. This paper describes the whole design process of the algorithm units in I frames of H.264 video compression encoder. The system uses FPGA as hardware platform and Quartus II, ModelSim as software platform to implement the algorithm units.Firstly, the paper introduces the H.264 encoder block diagram and the relative algorithm units, and then provides some tutorials on the key algorithm units in I frames, gives the implementation details, and makes an analysis of the relative simulate waveform. In the end, the paper provides the testing methods of the algorithm units.Integer transform is multiplication-free. Quantizer adopts the simplification algorithm, and no need for division operator. Scanner is in Zig-Zag order. Entropy coding uses context-based adaptive binary arithmetic coding(CABAC).