Mobile Communication If Digital Receiver Design And Implementation

In the traditional communication systems, the demodulator modules in receivers always realize in analog processing methods. The key performance parameters in these systems tend to have a strong dependence to devices, which results in less flexibility and incomplete advantages of the digital communication system. Software radio has brought the emergence of innovative ways to implement receiver. All-digital receiver based on software radio can easily cope with the traditional technology's challenges. In today's mobile communication systems, digital receiver plays an increasing important role.The mobile communication technologies develop rapidly and the 3rd generation communication system has begun to use widely. The topics covered in this dissertation are aim to adapt the fast developing requirements of modern mobile communication system. In view of TD-SCDMA standard, we has designed and realized a digital IF receiver based on the basic thought of software radio.This dissertation studies the basic theories and realizable methods of digital IF receiver, such as bandpass sampling and sampling rate transform. In addition, the realization methods of orthogonal mixer and numerically controlled oscillator are discussed in detail. Further more, this dissertation canvasses the familiar high-efficiency filter arithmetic and the optimizing means of filter implementation. With reference the current mainstream digital receiver chip structure of the premise, this dissertation presents a new orthogonal mixer structure based on broadband IF sampling.The main achievements and contributions of this dissertation are as follows:1. Research and demonstrate the TD-SCDMA system digital IF receiver's design and implementation methods.2. Based on wideband IF sampling software radio architecture, design and realization the key modules such as orthogonal mixer, numerically controlled oscillator, decimation and digital match filters.3. Propose a new orthogonal mixer structure. This structure saves the logic resources within FPGA, and reduces system cost, enhances system flexibility and scalability. 4. Propose the system design and key modules optimization methods for IF digital receiver. According to these methods we has implemented the IF receiver and gave the test results.