Software Radio Receiver Digital Down Converter In The Design And Realization

The research of using FPGA to design and implement is done in this paper. In this paper, we focus on the design and simulation of the important function modules. And the system simulation is done after all the functional modules were designed. The aim of this project is to design a single channel Wide-Band Digital-Down-Converter (DDC). This DDC will work as the front-end of the channelizing module which we designed before, for changing the data rate between the ADC and the channelizing module. The output of the DDC is 2.56MHz and the pass-band is 2MHz, the stop band attenuation is greater than 70dB.Based on the study of DDC's framework and the theoretical knowledge, we analyzed the relationship between performance and the functional models. The framework had taken the AD6636 and HSP50214B for reference. The top-down design flow is adopted to perform the system designing and budgeting. The main critical modules had been coded, synthesized, simulated and implemented.Based on the character of the Software-Defined Radio (SDR), we designed a SDR hardware platform. The ADC is usedthe Linear Technology's LTC2208 and the FPGA is used Xilinx's chips XC4VSX35. And also reserved a large number of test interface. The hardware test is taken on this platform. Due to the complexity of the system design and limited of the time, we only finished the DDC's main function module and the hardware also had some problem to solve.