High-power Multi-chip Component Thermal Analysis And Thermal Resistance Technology

Multi-Chip Module (MCM) technology attracts much more attention in researching and developing microelectronic packaging technology because of its special characteristics, such as small volume, high packaging density, high performance, high reliability and so on. The heat in MCM tends to be higher, which will cause thermal power density to increase gradually. This problem is particularly serious in high power or high density MCM. Therefore, thermal analysis and thermal design technology become critical for MCM technology.Traditionaly, chip temperature under different environments or output power can be gained from some unconvenient ways such as practical measurement or computer simulation. It is very necessary to precisely predicate the devices'thermal characteristic under different conditions for improving the reliability of devices and accelerating the thermal design progress.According to the problems of thermal failure and lack of thermal evaluation ways in high power MCM, the researches of thermal simulation, thermal analysis and thermal resistance of DC/DC convertor were presented in this paper.1. A parameter finite element model of power convertor was built by ANSYS 9.0 and thermal field was analyzed. The error between simulated value and practical measured value is about 2%, which verifies the validity of finite element simulation technology.2. The thermal characteristic which was influenced by different environment conditions and packaging structure parameters, was researched and the thermal structure was optimized. The results show that: the device temperature changes linearly with the bottom board and environment temperature increasing. The relation between environment convective coefficient and device temperature is in inverse change. Device temperature can be reduced efficiently by changing the convective coefficient of the packaging material and packaging size. Improved thermal field and weakened thermal coupling can be got by arranging the chips'positions advisably. The best positions for D1, D2, D3, D4 and D5 are 6.3mm, 12.0mm, 2.0mm, 5.5mm and 8.0mm, respectively. The highest temperature of the module has been reduced by about 32% after optimizing thermal structure of the convertor.3. A single chip thermal resistance network model under independent boundary condition was founded, using response surface method. The maximum model errors are 0.0049% under isothermal conditions and 2.4225% under convective conditions. The validity of the building model method is proved by founding a PLCC thermal resistance network.4. The boundary conditions were set, according to actual working conditions of the convertor and design requirement. All of the thermal fields under different boundary conditions were computed. A thermal resistance of convertor power electronic module was built. Its maximum errors are about 0.9000% under isothermal conditions and 5.0000% under convective conditions. The maximum error between predicted values and measured values is about 4%.