Research On Thermal Resistance Of Power Device And Interconnect Structure Thermal Fatigue Of Power Module

Due to the development of high-density assembly of microelectronic devices andmicroelectronic system, per-unit volume power consumption of components is increasing.Increased power consumption often cause elevated temperature inside the package.Component will be unstable, when the temperature exceeds the rated temperature ofcomponents. In addition, due to different thermodynamic parameters, the interconnectstructure will failure under cyclic stress. In the paper, we studied the thermal resistance andinterconnect structures thermal fatigue problems of power devices VDMOS, which canprovide some guidance for the researches of actual thermal design and thermal fatiguedamage.We established the total thermal resistance from the heat source to the environmentbased on Laplace’s equation and the boundary conditions. The total thermal resistance consistsof two parts.The one is from heat source to chip and then to environment and the other is fromheat source to substrate and Kovar and then to environment. Then we calculated the totalthermal resistance based on parallel theory, and studied the influence of size of component,thermal conductivity, convective heat transfer coefficient on thermal resistance. The resultsshow that, the thermal resistance value decrease in nonlinear with the increase in device size;with the increase in thermal conductivity, the influence of thermal conductivity on thermalresistance is not the same as traditional theory, it shows a negative linear correlation; with theincrease of convective heat transfer coefficient, the influence of convective heat transfercoefficient on thermal resistance is the same as traditional theory, it shows a hyperbolicrelationship.In this paper, the finite element model was presented based on simplified physical model.We used the finite element software to simulate the temperature distribution of VDMOSunder the given boundary conditions; and measured VDMOS temperature distribution underworking conditions; then we calculated VDMOS temperature with thermal resistance model.The results show that the theoretical calculation and simulation results agree well with theexperimental ones.We studied thermal fatigue damage of VDMOS interconnect under temperature cycling conditions(-55℃~125℃). The stress and strain distribution of interconnect show that theapex of intersection of interconnection and substrate is prone to fatigue. Then, we adopted theimproved C-M model to predict the thermal fatigue life, which is908cycles.