Study On Thermal Resistance Of Power Electronic Package Based On The Finite Element Method

With the continuous requirement of people, power semiconductor devices have made great progress, particularly in the improving capability of handling high current and voltage, which result in the excess junction-temperature and related reliability problems due to the increasing power dissipation. Junction-temperature rise will not only lead to drift of electrical parameters of power semiconductor devices, but also affect reliability and life of the devices. It is of vital importance that during designing process thermal resistance of device package and external cooling condition should be taken into consideration to ensure that junction-temperature can be kept within a certain limit. Therefore, thermal resistance of device package is a critical parameter both for vendors and designers. This paper summarizes the related standards and methods for thermal resistance measurement of power semiconductor devices and studies thermal resistance of device package by modeling with finite element method.On the one hand, this paper describes the basic principle of thermal resistance measurement based on a document called JESD51 which was proposed by JEDEC in December 1995. According to the dynamic thermal measurement method with electrical parameters proposed in JESD51-1, junction-to-case thermal resistance and junction-to-ambient thermal resistance of devices with different types and packages have been get by using a thermal resistance tester called AnaTech Phase 11. A large number of test results show:Firstly, junction-to-case thermal resistance is related to area of chip, larger area, smaller resistance; Secondly, junction-to-ambient thermal resistance is related to volume of package, larger volume, smaller resistance; finally, junction-to-ambient thermal resistance is related to the structure of package including cooper frame and molding compound.On the other hand, finite element analysis by ANSYS is carried out to model the TO-220F package and do steady-state thermal simulation. With this model, this paper probes the effect of boundary conditions, area of chip, package size, type and defect of solder layer to thermal resistance. Simulation results show:Firstly, junction-to-case thermal resistance increase with smaller area of chip, smaller thermal conductivity and reduction in thickness of solder layer; secondly, junction-temperature rise with reduction in area of cooper frame; finally, void area and location in solder layer can also affect the junction-to-case thermal resistance. This paper suggests packaging manufacturers that reducing the volume of molding compound, choosing a reasonable kind of die attach and improving technology of die attaching can save costs without weakening the performance of devices according to the results obtained in the simulation.