The Realization And Optimization Of H.264 Intra Encoding Module Based On FPGA

As one of the mainstream video compression standards,H.264 has a very high compression rate and good network adaptability.So far,there are many open source projects to achieve H.264 encoding in the form of software,such as x264,JM,etc.Due to the high computational complexity of these software encoder,it is difficult to meet the requirement of real-time encoding speed that transferring them directly to ARM or other embedded devices.On the other hand,although the bottom operation of the H.264 is relatively complex,it is very suitable to hardware to achieve.Besides,with the development of the technology of integrated circuit,the parallel processing ability of FPGA is improved continuously.So the hardware implementation of H.264 encoder based on FPGA has became an import way to improve the encoding rate of the encoder on embedded devices.Because of the limited time, the paper only realized the intra part of H.264 encoder.On the basis of understanding the principle of H.264 standard and the FPGA development process, the paper realizes the intra encoder of H.264 by VHDL hardware description language. Besides, the 4 core modules(intra prediction, CAVLC, quantization and inverse quantization) of intra encoder are optimized, then the simulation and verification of them are carried out to prove the correctness of the operation. Finally, the overall performance of the optimized system is analyzed and tested, compared with the software encoder and the optimized FPGA encoder. The last improved FPGA hardware encoder to complete a macro block prediction average need to consume 50 clock cycles. The encoder run in the FPGA device with the clock frequency of 100 MHz, so it average need about 500 ns to complete a macro block of encoding. A total of 57600 macro blocks of a frame with a 720 p resolution,and a frame of the encoding is about 28 ms. Therefore the theoretical analysis that the average encoding rate FPGA encoder of 720 p video for 35.7f/s, to achieve real-time rate the requirements of 30f/s.