Fpga-based Dvb-s Channel Coding And Modulation

DVB-S (Digital Video Broadcasting by Satellite) modulator is one of the digital headend devices compatible with DVB-S standards, which can be extensively applied to satellite-specific digital video broadcasting and related services. In this article, the author mainly expounds on the FPGA-based DVB-S modulator channel coding and modulation, including function-based module decomposition and interface definition, as well as module-specific analysis of working principle and algorithm, HDL description, timing simulation and FPGA realization. Channel coding and modulation is the core of DVB-S modulator. By virtue of FPGA's advantages in digital signal processing, the paper gives detailed analysis on the realization of algorithm for several key modules, including RS coding, convolutional interleaver, and punctured convolutional coding, and the algorithm is verified by HDL description and timing simulation. Moreover, The resources of the FPGA modules are estimated, and the internal PLL of Altera's Cyclone devices is employed to receive ASI signal. From the test, it shows that the DVB-S modulator technical specifications defined in this article have reached the design requirements.