Research Of QC-LDPC Encoding Algorithm In WIFI System And Its FPGA Implementation

The full name of LDPC code is low density parity check code, it is a kind of linear block code and is widely used in the area of communication, LDPC code is also adopted by several communication standards. It has the outstanding performance to approach the Shannon limit, just like the Turbo code. The check matrix of LDPC code has the properties of sparseness, which reduces the complexity of the encoding algorithm. In the mean time, QC-LDPC code can be obtained by operating cyclic shifting to the basic matrix, this makes the QC-LDPC code has the cyclic property. The cyclic property reduces the storage space to store the check matrix during the encoding/decoding process, which makes the encoding/decoding process simplier.This article is about to implement the data transmission based on the WIFI system, this transmission needs a high throughput and high clock frequency, a lower bit error rate and acceptable resource consumption. To solve this problem, in this article the Efficient encoding algorithm of LDPC code is chosen, and the algorithm is implemented in hardware, the quantifiable outcomes are given at the end of the article.At first in this paper, the background and significance of the research on the LDPC code is introduced. The present situation of the research is also referred. Then we make introduce of the channel coding, which lays a foundation of the coming chapters.In the second chapter, we provide the concept of linear block code, summarize the theory of LDPC coding/encoding, including the representation of the LDPC code, the classification of the LDPC code and the construction method of the check matrix. Several methods to make the LDPC code has a good performance on error correction is also involved. The decoding algorithm is introduced afterwards, namely belief propagation algorithm.In the third chapter, a typical encoding algorithm of the LDPC code is presented. After the calculation of the encoding complexity of the algorithm and the analysis of the demand of our system, also consider the resource consumption, we chose the efficient encoding algorithm. The encoding complexity of the efficient algorithm is calculated. At last, the simulation under different code rate of the simplified efficient algorithm is given.In the fourth chapter, we work out the design scheme of the encoder for the simplified efficient algorithm. The design and hardware implementation of each sub module is also given. The encoder could work under different code rate, and it has a high throughput.In the last chapter, we finish the test and verification of the encoder. In the procedure of verification, the message after encoding is transferred to the PC, the correctness of the encoding is verified through Matlab.The QC-LDPC encoder designed in the article can meet the design targets below: input 32 bits, output 96 bits, stable clock frequency 200 MHz, maximum clock frequency 250 MHz, maximum data path delay 3.761 ns, throughput 5Gbps, bit error rate 10-7(2304bit code length, code rate 5/6, 3d B SNR, BP decoding algorithm), all the targets could satisfy the demand of the system.