Research On Channel Encoding And Decoding Technology Based On FPGA

With the rapid development of the information age,the requirements for the reliability of information transmission are getting higher and higher,and channel coding technology has gradually become a hot research area.Current channel coding technologies include traditional convolutional codes,RS codes,and Turbo codes,as well as newly developed low-density parity-check code(LDPC)codes,polar codes,and so on.Because the LDPC code has excellent error correction performance and is close to the Shannon limit,the LDPC code is used as a channel coding scheme in many communication standards.The LDPC code is a special linear packet error correction code,which uses the check matrix to compile code,and the check matrix has only 0,1 elements,which is sparse.Compared with other coding methods,the LDPC code coding method is easy to analyze and study,and the hardware implementation can achieve higher throughput and lower error leveling.LDPC codes have great research value and significance.This article makes a brief analysis of the current status of channel coding research.The basic principle of channel coding is described,the key technologies of WLAN are described,and the frame structure of the physical layer based on the IEEE802.11 ac standard is introduced.The description methods,coding process and decoding process of different channel coding methods are introduced.Based on the different construction methods of the check matrix,several different encoding methods of the existing mainstream LDPC codes are analyzed and introduced,and the detailed propagation derivation algorithm is derived.Based on the IEEE.802.11 ac standard,the performance difference of different decoding methods under MATLAB simulation is analyzed,and the decoding performance of different iteration times in the BP decoding algorithm is compared.Finally,it is proposed to complete the design of the encoder by using the coding method based on the approximate lower triangle.Using the particularity of the check matrix structure,the check matrix is subjected to elementary transformation.The improved minimum and BP decoding algorithm is used to implement the decoder solution.In the performance simulation results,the improved minimum and BP decoding algorithm is not as good as LLR BP in performance,but it is convenient for hardware design and implementation.In the core module,serial decoding is used for the check node update unit and the variable node update unit,which reduces the decoding complexity and saves the logic resources of the FPGA.Through the analysis of simulation results,the feasibility of the scheme on FPGA is verified.