| According to the development of information technology, high-speed and large-capacity of data storage is required in the field of communication and radar. In the control system, data cache memory is often used in high-speed data acquisition, because microcontroller and general bus can not manage the output of high-speed data in time. In large-capacity continuous data memory control system, using SDRAM (synchronous dynamic random access memory) with the characteristics of high integration, low power, high reliability, and strong function is the best choice. But SDRAM need to refresh timely and has complex time sequency compared to SRAM with high velocity and simple control. To decrease system cost, we design and realize SDRAM controller by FPGA and Verilog HDL.In the paper, the principle and characters of memory are presented; the struction and constitution of SDRAM controller are introduced. The concept and configuration scheme of FPGA are shown, and verilog HDL are given. To the question of SDRAM fixed inner character, the paper designs schemes of two-way interleaving and bank interleaving, so the conflict between auto refresh and data reading/writing is solved well, also is the conflict between percharge and data reading/writing. We can easily meet the need of high-speed continuous data storage. The paper also designs the hardware interface circuit which is realized by Large Scale Integrated circuit, and analyses the state shift processing in handling SDRAM. The controller of continuous storage is realized by verilog HDL, and the interface to PC can be transparent to the user. The development background, the establishment of whole structure, hardware design and software design are expatiated. The paper shows large-scale application of this continuous storage broad, and the shortcoming of the system is presented in the end.The whole work of article completes the designs of hardware circuits and the program and debug of software in Verilog for SDRAM controller in controller system. This supplies a template for high-speed data acquisition of control system in the future. |
