High-speed Digital Test Module Vxi Message-based Interface And Module Driver Design

The Master Dissertation was written with the task that I had accomplished in the project of"the Design of High Speed Data Testing Module Based on VXI Bus"for 14th research institute of Nanjing.VXI high speed data test module provides 64 bidirectional TTL pins, a properly designed test serial controls an I/O pin. As an VXI equipment designed for testing complex data system, it wins through the shortcomings of traditional test method which uses signal generator to supply stimulus and utilizes logical analyzer to sample response data. It can achieve complicated cooperation between stimulus and response by sampling response data in the single period and then comparing it with the expectation data while imposing test stimulus on the test objective. The comparison result is the base of real time branch, through real time comparison and branch, the tester can obtain the test structure as do-while and if-then-else, which can provide powerful support for quick error check and fault location, thus embodies some intelligence during the test course and greatly improves the automation degree of the test system. To simplify the generation course of test serial, the module supplies"learning"function ,that is , the tester can sample the response as standard answer from the fault-less system and transfer it into corresponding standard test serial automatically and impose it on the object system, then conduct real time comparison between the obtained response with the standard one. Meanwhile, The"learning"result can be uploaded to PC via plesio-FDC (fast data channel), so to supply model for the consequent test serial. The task in the paper comprises two parts. The software design procedure works as follow, program the drivers for module on PC with CVI , generate the corresponding DDL and then edit the test serial and invoke the DDL by designing soft panel with VC++6.0 .thus facilitate users to control module to conduct high speed data test. The hardware design procedure works as follow, design VXI message based interface circuit and plesio-FDC circuit with fast data transport function on XC2VP30, a Virtex-II Pro series FPGA chip designed by Xilinx company which integrates Power-PC processor. The approach of designing interface circuit and plesio-FDC circuit with FPGA...