.10-bit 500mhz Sampling Rate Cmos Dac Design

DAC has been applied in many fields, such as computer, communication, military affairs and digital signal processing(DSP) and so on. The recent growth of the wireless communication and the mixed-signal market has made the interface between the analog and digital part of the system one of the key building blocks of the integrated system design. High performance digital-to-analog (D/A) converters find applications in the areas of video and wireless communications, such as HDTV and GSM. So, it is useful to make a careful study of high-speed DAC.A 10-b, 500-MSample/s DAC that was based on the 10-b, 200-MSample/s DAC of IP Goal has been designed. During the design, the full-custom design method was followed: confirm the spec-circuit design-simulation- layout design-tap out. The main results are as follows:1. Voltage DAC, current DAC and capacitance DAC are investigated in detail. Their working principal, advantages and disadvantages will be discussed. According to their characteristics and the design objective. the current hybrid DAC architecture that consists of a 5-bit binary and a 5-bit unary was selected.2. The control signals couple through the capacitance of the switches to the output, the dynamic error caused by the parasitic gate–drain feedthrough capacitance is significantly lowered by the use of a reduced voltage swing at the input of the switches. At the same time, it is nessary to shift the crossing point of the switch transistor's differential control signals, in such a way that these transistors are never simultaneously in the off state.3. The mismatching of the current source transistors is investigated in detail. To obtain a high resolution CMOS current-steering digital-to-analog conveter, the matching behavior of the current source transistors is one of the key issues in the design. In the design, a gradient-error and endge-effect tolerant switching scheme for 10 bit DAC is presented. we explain how to select the dimension of the unit current source transistor and why this scheme has those properties and how to construct it.4. The noise of the substrate and the inductors of the pads are investigated in detail.