The Design Of A Kind Of Low-voltage And High-accuracy CMOS Operational Amplifier

With the development of People's life-style, kinds of electronical products have been required more and more hard, as a result of the electronic test survey in the medical field ,the automobile electron system, the military astronautics domain's widespread application, it's eager for the use of the CMOS low voltage high accuracy operational amplifier to enhance the accuracy of the electronical products. It need to magnify processing for the weak signal in the test survey, therefore it became necessity that the high accuracy operational amplifier is studied inevitably, which advanced the development of the high accuracy operational amplifier.The thesis has done the widespread investigation and study to the domestic and foreign technologies of analogy low voltage, and analyzed the principles of work, merits and short comings of these technologies. It designs a high accuracy operational amplifier. This article mainly aim at reduces the input offset voltage to launch the research and design operational amplifier. The structure of input stage adopted folded-cascode. In order to reduce the twinkle noise, the input differential stage used PMOS tube. Simultaneously the bias current mirror load of folded-cascode differential input stage was offered by the wide swing cascode which can run under low voltage normally. The PMOS tube common source amplifier was adopted in the gain stage for the sake of reducing the twinkle noise. When designing output stage, in order to enhance the efficiency, it uses the push-pull common source stage amplifier as the output stage, the output voltage swing basically reached the supply voltage. The normal source of the thesis adopted use the traditional normal current source based on the operational amplifier. In order to work stability the amplifier uses the Miller compensate technology with an adjusting zero resistance to compensate the operational amplifier. In order to reduce the offset voltage, chopping technology has been adopted.The circuit design is realized in CSMC 0.35μm CMOS technology and HSPICE simulation results of CMOS indicate that it's offset voltage only 18.7μV, achieves the dc open gain of 88 dB, unity-gain frequency of 2.5 MHz, and the phase margin of 80°in 1.5 V power supply. The main pre-defined specifications are satisfied with the simulation results.