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The Soi Step Doping Ldmos Design And Experiment

Posted on:2007-09-12Degree:MasterType:Thesis
Country:ChinaCandidate:Q W LiuFull Text:PDF
GTID:2208360185955694Subject:Microelectronics and Solid State Electronics
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SOI HVIC (Silicon On Insulator High Voltage Integrated Circuit) is the mainstream and trend of the Power Integrated Circuit (PIC) due to the improved no latch-up, reduced leakage current, perfect irradiation hardness, and improved insulation. As one of the key device in SOI HVIC, SOI lateral high voltage device has been deeply investigated in this field. In lately 20 years, many new structures and technologies have been developed. However, the tradeoff of breakdown voltage with specific on-resistance is always being researched.This thesis was supported by the key Program of National Natural Science Foundation of China. In this thesis, the optimization of SOI step drift doping profiles LDMOS is addressed. The work of the author included the optimization of SOI Single-RESURF LDMOS and; design and implementation of a step drift doping profiles SOI LDMOS.The research of the effect of SOI S-RESURF included the impact of the geometry parameters and drift doping concentration on breakdown voltage and on-resistance. Author analyzed the relationship between the length and the impurity concentration of drift region and thickness of buried oxide layer and thickness of SOI and the charges of oxide layer and bias voltage of bulk and breakdown voltage and on-resistance by numerical simulation. The result of numerical simulation indicated the tradeoff of breakdown voltage and on-resistance. The selection of structure prefer the thicker buried oxide layer and the thicker SOI layer and the shorter drift length when the breakdown was happened at the interface of SOI and buried oxide layer.It is represented the optimization and implementation of step drift doping profiles SOI LDMOS. Theory analysis, numerical simulation and experimental result indicated that the surface electric field of the device was more uniform and the breakdown voltage was increased effectively. In the layout design of the power device, a circular structure was adopted to avoid the spherical junction and reduce the curvature effect. In the design of the device, a kind of junction termination technology, polysilicon field plate was introduced at the edge of source and drain of the device. It reduced the electric field of PN junction and NN+ at the surface to avoid breakdown at the two points. In the...
Keywords/Search Tags:SOI LDMOS, step drift, breakdown voltage, on-resistance
PDF Full Text Request
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