Research And Development Based On Nios Ii System Of A Single Ts Stream Multiplexer

Our country has already begun to start up the whole transformation of Cable TV from the Analog to the Digital.The age of China's"Digital Television"has already commenceed. The development of Digital Television is facing a unprecedented opportunity. Moreover, there are two superiority of the bandwidth and speed in the existing Cable Television Network. Therefore the equipment manufacturers and the service providers must first consider how to fully make uses of the band resources of the Cable Network,and develop Integrated Services Digital Network of multimedia. The MPEG-2 TS Mulitplexer is a essential equipment in the Front End of the Digital Television System. Therefore there is the huge economic benefit to research and develop TS Multiplexer.In the dissertation author first analysis and research MPEG-2 standard in detail, and carry on the theoretical analysis and the hardware realization research of two essential technique -PCR adjustment and CRC-32 algorithm. Then author put forward a kind of project of TS multiplexer based on NIOS II system. This is one kind project of hardware Multiplexer based on the high-performance system on a Programmable Chip (SOPC).In the project author integrate with the software and the hardware on a Field Programmable Gate Array (FPGA),Not only simplifying the overall system design,moreover realizing stably, high speed, low cost Multiplexer's design.The dissertation carry on three verification step that include function verification,time verification and prototype verification to guarantee each IP can work normally to satisfy the system performance requirement.Then author introduce the realization of the Multiplexer in detail,as well as the test and the debugging questions met in practice and solution of the questions. Finally author make the summary analysis of the dissertation.There are several primary contribution in the dissertation:(1) The dissertation improved on the traditional PCR correcting method so that the correcting precision is smaller than 100ns(≤500ns in the standard), and reduced the logical resources use greatly.(2) The dissertation adopted a kind of the CRC-32 method of FPGA implement...