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Home Relegation Low-power Intelligent Leakage Protection Design Of The Chip

Posted on:2007-10-23Degree:MasterType:Thesis
Country:ChinaCandidate:Z WangFull Text:PDF
GTID:2208360182970767Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
China now has the biggest share in the market of residual current protector, but only the biggest, not the best one. This is a heavy burden for those Chinese factories that have to buy these chips from a few foreign companies, and so they cannot earn too much money from the heavily competitive market.This author in this paper introduces a new type of residual current device that can be the substitute of M54133FP/GP. Unlike M54133FP/GP, this chip is achieved in the process of mixed-signal CMOS, but not purely analog bipolar process, which means it can take the full advantage of logic design: the flexibility in logic function and low power in dissipation. Some features of this chip are listed below:The first, "the fixed response delay time" concept insure that the response time is set according to the amplitude of the input signal of leakage current which can be more effective to prevent human being from hurting. For example, if the value is larger than 2I_n and smaller 4 I_n, the response time will be set to 120ms..The second, using the digital circuit to realize the time control replacing the RC circuit, which can be more accurate.The third, the judgment block is implemented in digital circuits for the validity of the input signal, which will reduce the miscarriage of justice greatly.The fourth, the function of over-voltage protection for the power supply are integrated in this chip beside the residual current protection, so this chip acts like some of power management.The fifth, the power consumption is only 5mA with 200mA of M54133FP/GP.The chip is a mixed-signal chip. This chip joined the MPW plan laughed by ICC, it was taped out in Shanghua Semiconductor corp., Wuxi. It is processed in 0.6um double metal, double polysilicon, twin well CMOS process. The test chip area is 4mm~2 with 28 test pins.
Keywords/Search Tags:Intelligent
PDF Full Text Request
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