Research On Reconfigurable Computing Unit For Application Domain

A novel application-specific reconfigurable computing method is proposed in this thesis to overcome the weakness of existing target architectures. A reconfigurable computation array for communication applications is designed, which implements Chip Rate Processing (CRP) algorithm in OFDM system and Fast Fourier Transform (FFT) algorithm. After the design of computation array, software flow that maps algorithms into the computation array is developed based on FPGA software flow. A set of algorithms whose implementations are characterized by data-driven, simple controlling logic and parallel computing properties can be mapped into the proposed array. In this thesis, design of reconfigurable Fast Fourier Transform processor and computation array is presented as well as flow of algorithms mapping which is also referred to as computing tasks mapping.Existing FFT decomposing algorithms and hardware architecture have been studied, based on which a radix-2/22/23/24decomposition is proposed to reduce the number of full complex multipliers. As proposed FFT decomposing algorithm is balanced, the memory consumption used to store twiddle factors is minimized. In addition, a constant multiplier sharing strategy is proposed to reduce the number of constant multipliers in FFT processor. The area-efficient implementation of proposed sharing strategy adopts the Multiple Constant Multiplication and Reconfigurable Multiple Constant Multiplication techniques and consumes the least number of equivalent adders compared with existing results. A reconfigurable FFT architecture able to calculate128to8192-point FFT is proposed by employing radix-2/22/23/24decomposition and constant multiplier sharing strategy. As a proof of proposed FFT architecture, a reconfigurable FFT processor for DVB-T/H application is designed. To design computation array, chip rate processing algorithm in UMTS system is studied. According to the analysis of FFT and CRP algorithm, the set of fundamental coarse-grained atomic operations are defined. Computing units and interconnection among these computing units are designed to make up TILE, the data processing units of computation array. Reconfigurable memory block are designed to store data and configuration circuit designed to reprogram the array.Reconfigurable FFT processor for DVB-T/H application is designed and synthesized under SMIC0.13um technology, whose peak operating frequency is34MHz and logic count is38K equivalent NAND2logic gates without memory. The computation array supports FFT ranging from128-point to8192-point and CRP. FPGA-based software flow is developed to model processing units in the array and generate binary configuration bits to map algorithms into the computation array.