RLC Parasitic Parameter Extraction And Reduced-Order Modeling Of High-Frequency Transmission Lines

With the continuation of Moore's Law and the rapid development of semiconductor technology, the integrated circuit chip size is getting smaller and smaller and signal frequency is getting higher. With the emergence and the large-scale applications of SOC, the chip interconnects are becoming more and more important. As chip scale is getting bigger while the line width is getting narrower, the main signal delay in IC comes from the line delay instead of gate delay. The effect of interconnection transmission lines is becoming bottlenecks of whole system performance.Thus the study of transmission lines is becoming increasingly important. But in today's technology and signal frequency, the traditional lumped parameter extraction method gradually becomes inaccurate because of the parasitic effect introduced by high frequency. So finding new parameter extraction methods and new-models to meet the current needs of process conditions and the signal frequency is of paramount significance.In this thesis, the author has studied one high-frequency parasitic parameters extraction method and proposed to apply a low-order modeling technique for frequency-dependent interconnect modeling.The thesis consists of two parts:Interconnect parasitic parameter extraction Considering the high frequency skin effect on the transmission line, in order to make the current density of each segmentation uniform, the segmentations of section are in certain proportion. And after segmentation, parasitic parameters R L C are extracted in order to achieve the equivalent RLC network matrix.Model order reductionAs interconnect of chip getting loner and longer, the generated matrix becomes bigger. So it's necessary to use module reduction to simplify the matrix. In this thesis, the author uses MOROC module order reduction method to get simple and effective model form RLC network of transmission line.