Research On Order Reduction Analysis And Optimization Techniques Of Integrated Circuit Interconnect In Very Deep Submicro

Interconnect system in VLSI is complexity, and the mutual coupling is large.So, the equivalent circuit of interconnect wire scale usually reaches tens ofthousands to hundreds of thousands orders. Tranditional circuit simulation tools cannot achieve the effective analysis on such a large interconnect circuit. Thus，It is thefundamental problem of performance analysis and optimization of IC to solve rapidanalysis of large-scale interconnect circuit. Moreover, interconnect parasitics haveincreasing influence on integrated circuit performance, which increases the ICdesign pressure. Interconnect optimization techniques are a kind of effective meanto solve the problem of interconnection. Hence, this thesis mainly studies twoaspects those are the integrated circuit interconnect model order reduction (MOR)analysis and interconnect performance optimizaiton technology.In space projection MOR aspect, we have proposed MOR method basedgeneralized inverse in Krylov sub-space, MOR method based swarm intelligencealgorithm, and parameterized MOR method based general structure preservingtechniques. On the basis of traditional orthogonal projection and oblique projectionor Galerkin space projection and Petro-Galerkin projection, we proposepseudo-inverse projection method in Krylov subspace, which satisfies minimumnorm least squares projection condition that is relative optimal reduced order resultin the sense of space projection reduced order. For traditonal structure preservingMOR problem that do not maintain the structure of inductance incidence matrix inreduced order process, we propose a MOR method based a swarm intelligencealgorithm that turns structure preserving reduced order process into parameteroptimiztion process and then optimizes it. On the basis of local uniformitycharacteristics of interconnect wire, we propose a parameterized MOR methodbased on general structure preserving techniques that can effectively retain theprobability characteristics of parameterized interconnect system. Simulation resultsprove the correctness and effectiveness of all above methods. Finally, For the globalerror bound prolem of space projection reduced order methods, we propose fourtypes of error bound calculation methods in time domain.In orthogonal funciton approximation reduced order aspect, we have proposeda weighted self-adaptive threshold wavelet for interpolation point selection MORmethod and a Chebyshe-Wavelet reduced order method. Weighted self-adaptivethreshold wavelet for interpolation point selection MOR method is on the basis ofrational Krylov MOR by weighted self-adaptive threshold wavelet method to selectrational frequency interpolation points. From simulation results, the precision of MOR based weighted self-adaptive threshold method is higher than man-madethreshold method. For Chebyshev function approximation reduced order precisionlimitation in local approximation and4-order B spline wavelet reduced ordermethod speed problem，we propose a Chebyshev-Wavelet MOR method that makesthe fullest use of Chebyshev-Wavelet function to construct wavelet functionexpansion MOR method, which considers reduced order speed and precision. Fromexperiment results, the speed of Chebyshev-Wavelet method is highe than4-order Bspline wavelet method and is same with Chebyshev method. While the precision ofChebyshev-Wavelet method is highe than Chebyshev method and is same as4-orderB spline wavelet method.For the circuit level optimization aspect of interconnect system, we havestudied a buffer insertion method in parameter variation condition and low powerprocess variation-insensitive current-mode signaling scheme respectively. Inparameter variation buffer insertion fact, we have propsed a probability methodbased on Gaussian fitting, which mainly used Gaussian function fitting the jointprobability density of inserting wire and buffer. From simulation results, we canprove the correctiveness and effectiveness of the method. In the low power andprocess variation-insensitive current-mode signaling scheme, we have proposed anew current-mode circuit that mainly used a biasing circuit based on self-biasstructure to maintain process variation robust by compensation strategy. Fromsimulation and testing results, we can prove that interconnect system delay onlychanges very little due to process variations, while the power of current-modecircuit is reduced effectively.For the structure and system level optimization aspect of interocnnect system,we have proposed a time division multiplexing FV-BI bus coder based on data buscharacteristics. FV-BI coder can effectively improve the switching activity of thecase that is consecutive transmiting two uncoding data in data bus. Due to usingtime-divison multiplexing technology, it only need to introduce one additionalsignal line. Moreover, it can employ small area and consume less power by usingregister sharing technology. From simulation results, we can conclude that FV-BIcan improve26.4%switching activity in random data than FV coder. Meanwhile,we also propose a system level buffer model and a fast speed timing analysisoptimization method which can be used in system level timing analysis andoptimizaiton in normal condition and process parameter variation condition.Simulaiton results prove the correctiveness and effectiveness of it.