Research On High Performance Cache And Memory System

With the processor-memory performance gap continuing to grow, the performance of memory access becomes the major bottleneck of the performance improvement for modern microprocessors. It becomes a hot spot of research activities to propose new cache and memory control mechanisms and policies in order that processor-memory gap will be decreased.Based on investigations of memory access behavior, through experimentations of SPEC CPU2000 benchmarks running on Godson-2 processor, several policies that can improve performance of cache and memory system significantly are proposed and evaluated in this dissertation. The proposed techniques can increase memory access bandwidth while decrease access latency so that IPC of the processor is increased. Following contributions are presented in this dissertation.1.Cache adaptive write allocate policy that improves the bandwidth of microprocessor significantly is proposed by investigating cache store misses. Cache adaptive write allocate policy collects fully modified blocks in miss queue. Fully modified blocks are written to lower level memory based on non-write allocate policy which can switch to write allocate policy adaptively. Comparing with other cache store miss policies, cache adaptive write allocate policy avoids unnecessary memory traffic, reduces cache pollution and decreases memory queue full rate without increasing hardware overhead. Experiment results indicate that on average 62.6% memory bandwidth in STREAM benchmarks is improved by utilizing cache adaptive write allocate policy. The performance of SPEC CPU2000 benchmarks is also improved efficiently. The average IPC speedup is 5.9%.2.Adaptive stack cache with fast address generation policy is proposed by investigating stack access behavior of programs. Adaptive stack cache with fast address generation policy decouples stack references from other data references, improves instruction-level parallelism, reduces data cache pollution, and decreases data cache miss ratio. Stack access latency can be reduced by using fast address generation scheme proposed here. Adaptive stack cache with fast address generation policy can also avoid unnecessary memory traffic. Stack cache can be disabled adaptively, when it is overflow. It can also be applied to multithread scheme by adding thread identifier. Our experiment results indicate that about 25.8% of all memory reference instructions in SPEC CPU2000 benchmarks are executed in parallel by adopting adaptive stack cache with fast address generation. On average 9.4% data cache miss is reduced. The performance is improved significantly. The average IPC speedup is 6.9%.3.Prefetching policy using miss queue information is proposed by investigating instruction cache misses and data cache misses. The prefetching policy increases the efficiency...