Multi-machine Interconnected In The Smp Environment

The work in this thesis bases on the part of the Pre-research of National Defense project - SoC Application in Next Genneration of Airplane.With the development of VLSI, the performance of microprocessor improves continuously. But new larger applications ask the better computer system. The SMP multi-processors system building by RISC microprocessors is one of the methods of high-performance computer."LongTengRl" is a high performance 32-bit microprocessor we developed last year. It has five parts, such as Integer Execution Unit, Floating Point Unit(FPU), Instruction Cache, Bus Interface Unit and Memory Manage Unit. The instructions are executed with pipeline way. The Instruction Set and I/O signals are compatible with PowerPC. It is typical RISC microprocessor architecture.The first part of this thesis finished the Bus Interface Unit of "LongTengRl". It will become the basis of Shared Bus. Though the analysis about the PowerPC Bus, there are four parts in BIU: Instruction Pretreatment Part, Address Bus Treatment Part, Data Bus Treatment Part and Data Pos-treatment Part.The second part focuses on the Memory Consistency. It analyzes several methods about the Cache Consistency, especially the Bus Snooping Protocols. Basing on the "LongTengRl", this thesis completes design and realization the ?LongTengRl SMP" microprocessor.Though the comparing the PowerPC microprocessors, "LongTengRl SMP" sets its architecture, capacitance and policy of Data Cache. And it integrates with the logic of Bus Snooping. This part makes it be able to support SMP.At last, this thesis completes the function simulation of "LongTengRl SMP" multi-processors. And it discusses some development of the "LongTengRl SMP"."LongTengRl" microprocessor system is a complex system. "LongTengRl SMP" is one of the using aspects. This thesis hopes that it could provide an optional method for embedded microprocessor with full copyrights.