CMOS Rf Devices Modeling And Low Noise Amplifiers Design

Wireless communications has experienced an explosive growth in the last decade, which has made the research on high integration, low power transceiver become the hotspot in both academic and industrial area. The wireless products market has long been dominated by the hetero-junction or silicon based bipolar/BiCMOS technology because of their relatively higher characteristic frequency. However, the continual scaling of the CMOS technology has raised the characteristic frequency of deep-submicron MOSFET up to 20GHz, even exceed 100GHz, causing a revolution in the traditional situation in the wireless market, and making this technology an attractive candidate for signle-chip full integration transceivers.However, since CMOS technology was originally developed for the low frequency analog circuits and large-scale digital circuits design, one of the challenges of introducing CMOS technology into the radio frequency applications is the lack of accurate RF MOSFET models. Grounded on the main discrepancies between the BSIM3v3 model and the measurement data, this thesis proposed a macro MOSFET RF a.c. model based on BSIM3v3, by adding a physical based gate resistor and a substrate network. This model was then validated by the measurement results.Another barrier for CMOS radio frequency integrated circuit (RFIC) design is the inaccuracy of the existing MOSFET noise models. Both the famous van der Ziel model and the BSIM3v3 model cannot accurately predict the noise performance of the deep-submicron MOSFET at high frequencies. Based on the a.c. model proposed, this thesis introduced an improved MOSFET noise model including both the channel thermal noise and the induced gate noise, whose effectiveness was validated by measurements.A research on wide-band on-chip spiral inductors and transformers modeling was also performed in this thesis. By introducing the substrate coupling effects and distributed effects in the new proposed model, the discrepancies between the conventional inductor model and the measured data at high frequencies were greatly improved. The new models of inductors and transformers were then verified by the quasi-3D EM software.To demonstrate the feasibility in CMOS RFIC design, one of the key blocks in transceivers — low noise amplifier (LNA) was designed in this thesis. By investigating various of LNA topologies, two novel structures of low power LNA were proposed. One is the transformer coupled, folded cascade LNA, and another is the reverse folded cascade LNA. Through extensively discussions on both of the LNAs design, all of the main simulated performances were given in the thesis.Finally, the two proposed LNAs were implemented in the TSMC 0.25μm RF CMOS process. The main performance of the LNAs were measured with chip-on-board (CoB) measurement methodology.