Fpga-based Airborne Secondary Radar Hardware System

Secondary Surveillance radar (SSR) is a key equipment in Air Traffic Control (ATC) and military Identification Friend or Foe (IFF).Since very high reliability and stability is required in these two areas, SSR is a hot issue in Radar signal processing. The traditional SSR responders carried by airplanes are mostly composed of middle or small scaled integrated circuits, which have poor performance in their stability and reliability. What's more, it can not meet the requirements of high-density and large amount replies because of its limit performance of real time processing ability. In allusion to these defects, this thesis provides a new kind of hardware structure which is made up of FPGA and DSP. This hardware structure has much strongpoint, such as high reliability, easily being integrated, suitable for modular design, fast processing, capable of real-time processing many replies etc. In this project, the author is responsible for the hardware design of FPGA, whose functions are getting data from the double channels, producing the signal PSV and the side lobe restraining signal RSLS, calculating the orientation and distance of the airplane compared to the radar antenna, exchanging data with DSP, sending back the report to the upper board etc. This thesis analyzes the digital signal processing algorithm of the responder and its realization in detail. Furthermore, it discusses how to improve the reliability and consistency of the system and how to make full use of the FPGA resources. At the same time, it gives the HDL implementation of key modules and their simulation outcome.