Implement MELP Decoder Speech Synthesis Algorithm Based On FPGA

One of the most important and common services in the communication systems is the speech communication. The low-bit-rate speech coding technology is an important development direction and a hot topic of research in the field of speech communications. The algorithm of Mixed Excitation Linear Predictive Coding(MELP) achieves good quality at bit rate of 2.4kb/s, so the MELP has become one of the main reference algorithms for the other low-bit-rate speech coding algorithms which have been used in many speech communication systems, and theredore it plays an important role in low-bit-rate speech coding.So far, most implementations of the MELP algorithm have been carried out on different DSP processors. Field Programmable Gate Array(FPGA) has been developed rapidly in modern digital system and it has been widely used in digital signal processing. With the IP cores and DSP modules in FPGA have been widely used in digital signal processing, the research of speech coding technology based on FPGA platforms have been required by practical applications.The role of speech synthesis part in MELP algorithm is to reconstruct speech signal from the decoded speech parameters. Each module in synthesis part has its direct impact on the quality of synthesized speech. This thesis focuses on the implementation of synthesis algorithm of MELP based on FPGA platforms. First, this thesis introduces research status of the low-rate speech coding and several low-bit-rate speech coding models. Then it introduces the codec processes of MELP, focusing on elaborating each synthesis' module of MELP. Secondly, the FPGA platform and the ways of using them to design the specific algorithms are discussed.. Finally, on the basis of the C language program of MELP algorithm, C program code of speech synthesis has been rewritten with Verilog HDL and porting to FPGA platforms. The MELP speech synthesis algorithm ultimate can be completed on FPGA platforms.The bottom-up design procedure has been utilized while programming for speech synthesis section with the use of Verilog HDL. The underlying function of each module should be first modeled, such as multiplication, left shift function. Then the higher layer function modules of speech synthesis are modeled, such as adaptive spectral enhancement, linear prediction synthesis. MELP speech synthesis finally can be completed on FPGA platforms through establishing the layers of hardware models. In addition, much work has been done on the optimization of the designed algorithm modules written with Verilog HDL for FPGA platforms. Test module should be written for each programming after the programming is completed. The function of these programs can be verified by examining the results of post-synthesis simulation.The realization result performance has been analyzed. The design performance of this article is compared to the performance of Vivado HLS conversed from C language to Verilog program, good results gave been shown in two aspects of resource utilization and program processing time.