A RTL Implementation Of ADPCM CODEC

In this project, we implement the code and decode of audio data in hardware based on an ADPCM algorithm, which has been implemented in software by Intel Corp in 1992: At a sample frequency of 16KHz, the sampled data in a 16-bit signed linear PCM form, the data transmission speed is at 256kbps. But when encoded into 4-bit ADPCM form, it is transmitted at a speed of 64kbps. If the sample frequency is 8KHz, the speed of data transmission will be 32kbps. The needed channel bandwidth is also reduced accordingly. This processor only grants 16-bit linear PCM inputs. Since an Encoder and a Decoder are included, it can perform a channel compression and a channel decompression at the same time. Using a bypass module, it also can pass 16-bit PCM data out directly when need no compression. The master clock can be asynchronous with PCM data side clock or ADPCM data side clock. Using an 8-depth async FIFO solves the synchronization and exchange of data be-tween different clock domains. The data transaction protocol comes from the most basic work way of UART. When the master clock is 16.7MHz, the PCM side and ADPCM side clocks both are 2.38MHz, the results of simulation show that the latency from the Start-bit of PCM data inputting UART Receiver to the Stop-bit of ADPCM data outputted UART Transmitter is 14.3 us and the latency from the Start-bit of ADPCM data inputting UART Receiver to the Stop-bit of PCM data outputted UART Transmitter is 14.7 us. The difference between the compression time and the decompression time should be as little as possible is up to the mustard judged from the results. At the logic synthesis stage, we make some research on the principles of Logic Synthesis at first, then by utilizing TSMC0.25um process, choosing the worst case that the workable temperature can be high to 125 degrees centigrade and the supply voltage is as low as 2.25V, and introducing the wireload library for effectively simulating delay and power consumption of wire connection, and taking the same clocks as in simulation, the critical path is 15.3ns and the chip area is 0.395mm2.