Real-time Processing Research-based The Adsp21160 Broadband Radar Pulse Compression

The technique of pulse compression is widely applied in radar and sonar systems because it resolves the contradiction between action distance and differentiate. By the development of modern high-tech, the speed and capacitance of DSP chips have improved greatly. The digital technique of pulse compression signal colligation and generation becomes the tendency in today. The signal processing system of modern radar needs a great deal of operations to suffice for real-time. The operation magnitude is so great that single DSP can't meet the requirements. In the condition, we should choose the parallel processing system composed of several DSPs. Based on the theory of pulse compression and analysis of the arithmetic of pulse compression, the frequency-domain digital pulse compression of broad band radar LFM signal has been realized on the hardware platform of HHPC board with four general-purpose DSP chip ADSP21160s. The main content in this dissertation include:1． Analyzed the time-domain and frequency-domain characteristics of LFM signal. Analyzed the frequency-domain pulse compressing performance and compared it with the time-domain's. Based on the digital signal processing, The frequency-domain digital pulse compression of broad band(B=25MHz and B=12.5MHz) radar LFM signal has been realized on ADSP21160. 2．Have studied the parallel arithmetic of mass DSPs. Chose pipeline arithmetic by argumentation and realized it on the hardware platform of HHPC board with four chips of ADSP21160. 3．Have completed the test between pulse compression parallel system and clutter restrain system and the radar display. First, store the echo wave date containing clutter to the external memory SDRAM of one HHPC. The four DSPs reads date pipeline from SDRAM to complete pulse compression and transmits the processed date by Link Port to the other HHPC to complete clutter restrain. Finally displays the target number and orientation on radar simulator. 4. Have completed the test between pulse compression parallel system and the radar simulator. Radar simulator outputs two channel signals (I,Q),external trigger and external clock to A/D board. The A/D board samples the two channel signals date and stores the date to internal FIFO in the A/D board. The four DSPs on HHPC reads date pipeline by PMC port which connects with the A/D board and complete FFT,IFFT arithmetic to realize pulse compression.