Dvb System, The Rs Encoder / Decoder Fpga Implementation

Reed-Solomon code, a powerful error correcting code for burst and random errors, is widely applied to deep space communications, mobile communications, disk array, digital video broadcasting system, and so on. The serial-inversionless Berlekamp-Massey algorithm has been implemented in RS (204,188) channel coding and decoding circuits of DVB systems and validated by using FPGA.The inversionless BM algorithm in RS decoder is implemented with serial mode, which avoids the inversion computation and only needs 3 finite-field multipliers. Thus, the complexity of hardware implementation has been mostly reduced. A 3-level pipe-line processing architecture is also used in the hardware and the coding circuit in RS coder is optimized by using the characteristics of the finite-field constant multiplier. All these techniques improved much efficiency of the RS coder/decoder and reduce the resource in the RS coder/decoder.The results of P&R demonstrate that this design constructs a RS encoding/decoding circuit with a 3.2K internal FIFO cache embedded, at the scale of 46K gates. Its encoding and decoding speed are 66MHz and 47MHz respectively. This work has been validated in Spartan II series of FPGA from Xilinx Company.