Design And Implementation Of High Performance Finite Field Multipliers

The increasing use of cryptography techniques in various communication and computer systems has inspired many researchers to find ways on performing fast computations over finite fields, especially over large finite fields of characteristic two. The central theme of the thesis is an investigation of finite field computations and their architectures, particularly the irreducible trinomials and pentanomials. All the multiplier architectures proposed in this thesis are bit-parallel finite field multipliers which can improve the efficiency of cryptosystems significantly.The first proposal of high performance finite field multiplier is based on unbalanced modular reduction algorithm. This algorithm can achieve high efficiency when computing on a certain class of finite fields generated by f(x) = x~m + T(x) where deg[T(x)]<