Research And Implementation Of Galois Field GF (2~m) Multipliers

With the development of communication technology, users' requirements for communication systems are increaseing highly. Safe and efficient operation of communication systems are received more and more attentions.The theory of Galois field has been widely used in data communications, information theory, VLSI test, information security and other applications.In this thesis, the algorithm and design of GF(2m) multiplication are studied depthly.The method study, structure design, performance analysis and hardware implementation of GF(2m) multipliers are investigated in this thesis.On the basis of reviewing the research history of GF(2m) multipliers, a kind of matrix architecture for GF(2m) multipliers and its complexities are analyzed.Also, a dimension reduced method is proposed and three kinds of architectures are designed based on it. They are combination of serial and parallel architecture,the low complexity architecture based on dimension reduced method and the architecture with dimension reduced method iteratively used.Furthermore,the architectures above and their complexities are analyzed and compared.With the using of verilog HDL and FPGA,the hardware performance of different architectures proposed is verified.This thesis's main work and relative summing-up are as following:1.Based on the analysis of hardware design and implementation of matrix method for GF(2m) multipliers,an architecture is designed and its complexities are analyzed.2.According to the advantages of different implementations of GF(2m) multiplication,a combination of serial and parallel architecture for GF(2m)multipliers is proposed.It realizes the tradeoff between space and time complexities.Especially with the iterative design and pipeline design used,it can fit requirement under different conditions.3.For the space complexity of GF(2m) is large, a dimension reduced method is proposed, and two corresponding architectures are presented. One is the low complexity architecture based on dimension reduced method, which can low the space complexity significantly in the case of large value of m. The other is the architecture with the dimension reduced method iterative used, the architecture will save resource utmostly. Moreover, the former combination of serial and parallel architecture for GF(2m) multipliers is also an architecture based on this method.4.The performance of different architectures is analyed and compared. Also,to design the most efficient multipliers in GCM and ECC hardware implementations, the most efficient architecture is chosen in different situations.From the simulation results of ISE, it shows that the presented three architectures realize the tradeoff between space and time complexities and lower the consumption of resoureces at the same delay.