Research And VLSI Implementa- Tion Of Key Technology For OFDM Baseband In Wireless Multimedea Sensor Networks

Wireless Multimedia Sensor Network (WMSN) is a new type of sensor networks with sensing and transmitting image, video, audio and other multimedia, which makes use of OFDM of multi-carrier transmission in order to improve spectral efficiency and capacity of resisting multipath fading. It is benefit to improve reliability of data transmission in WMSN. Nowaday, however, the disadvantages of core circuits in OFDM systems, such as channel estimation, equalization, error correction and DFT are higher complexity for implementation, larger chip area and higher power consumption.Research status at home and abroad about channel estimation and equalization, error correction was summarized in the dissertation. Advanced technique of equalization and error correction in WMSN were discussed, and performance of channel estimation and equalization was discussed. The RTL hardware circuit of channel estimation and equalization and conca-tenated code were optimized. Logic function simulation, FPGA verification, DC synthesize, designed back-end layout, analyzed power consumption were finished. Analysis demonstrates the method is able to decrease greatly complexity of hardware implementation and power consumption. The main work and innovation in this dissertation are:1) Proposing a serial concatenated error correction algorithm with strong error correction ability adapting to WMSN. Improved interleaver with software input software output of row-column decomposition is used in the structure of serial concatenated encoder, which makes better performance in error rate in WMSN system under Gauss channel and genera-lized channel respectively.2) Improving a LMMSE channel estimation algorithm with low complexity and optimi-zed MMSE equalization algorithm in OFDM baseband system. Compared with complexity of traditional method, that of proposed algorithm is decreased to some extent to adapt to the requirement of WMSN.3) Designing application specific data operation format to solve the problems of data precision and complexity of hardware implementation. And multiplier circuit structure of part of the parallel architecture was improved. For implementation of float multiplier, compared with parallel architecture, its hardware resource decreases by 40%. For FFT implementation, a radix-2/4 butterfly processing unit architecture was proposed. Because of adders reuse, pipeline architecture and inserted middle registers, the amount of adders decreased by 30% and processing speed is increased to solve the problem of signal transmission real-time performance.4) Global reuse method is adopted to design the inversion unit in RS encoder and decoder, which decreases by 23.5% number of multiplying unit. Time division multiplex technology is adopted to design data transfer control circuit, which decreases by 20.8% number of XOR unit and path metric unit, satisfying the requirement of power consumption.Based on TSMC 0.13μm 1.2V CMOS technology, this dissertation finished an ASIC adapting to low power consumption and high speed WSN, whose data transfer rate is from 2 to 8Mbps, error rate is lower. The area of circuits of the channel estimation equalization, RS-CC code and FFT/IFFT circuit are 0.503mm2、0.435mm2 and 1.008 mm2, respectively. The power consumption is 2.46mW、4.29mW and 7.04mW respectively that are only 44.8% and 54.66% of total area and power consumption respectively. They meet the requirement of designed circuit. Test rusults for the WSN chip showed that the performance of chip satisfies requirement, which error rate is below 10-6@10dB SNR, under 4 operating modes in OFDM baseband transreceive system.